The central processing unit (CPU) of a large computer system basically consists of memory elements, combinational logic, and a clocking system. The memory elements are arranged in sets, sometimes called registers, corresponding to the word size used within the computer system. Between the sets of memory elements are combinational logic circuits.
At the end of a clock cycle, which is also the beginning of the next clock cycle, data on the output of the combinational logic circuitry is stored in a first set of memory elements. This data appears on the output of the set of memory elements, and therefore on the input of other combinational logic circuitry connected to the outputs of the first set of memory elements. This other logic circuitry performs the designed logic function on the data, and at the end of the clock cycle the output of this combinational logic is stored in a next set of memory elements, at least some of which may include a set of latches that provide input to the logic circuitry. This process is repeated as the computer system operates; that is, data is processed by combinational logic circuitry, stored, passed on to the next set of combinational logic circuitry, processed, stored, and so on.
One of the features that is employed in large computer systems today is a "scannable latch." A scannable latch includes a latch that can be converted to a stage of a shift register by the use of appropriate clock signals. The scannable latch allows the contents of the resulting shift register to be "scanned" by shifting out the contents for examination. The shift register, and therefore the latch, can also be loaded with new contents by shifting in new data. See, for example, U.S. Pat. No. 4,495,629. Circuitry for testing for timing faults in synchronous sequential circuits are also disclosed and discussed in Malaiya, Y.K. and Narayanaswamy, R., "Testing for Timing Faults in Synchronous Sequential Integrated Circuits," Paper 19.3, pp. 560-571, 1983 International Test Conference (CH19331/83/0000/0560$0100 IEEE). The advantages offered over these by the present invention include flexibility, ease of use and simple construction.
FIG. 1 depicts a known "gated-latch" circuit 10 in which the gated-latch output Q follows (i.e. is set to the same value as) the data input D while the gate signal G is "high" (i.e., at the logic high level). When gate signal G changes to "low", any further changes to Q are prevented, and Q retains its most recent value, even if D changes. The complementary gated-latch output QN is always set to the opposite of the Q output value.
FIG. 2 depicts a known "gated-latch with dual ports" circuit 12 in which the gated-latch output Q follows the first port data input D, or the second port data input SIN, depending upon whether the first port gate signal CLK or the second port gate signal S.sub.-- CLK is high. The output Q is prevented from any further changes when both CLK and S.sub.-- CLK are low, even if D or SIN changes. The complementary gated-latch output QN is always set to the opposite of Q. If both CLK and S.sub.-- CLK are high while D and SIN have opposite values, the latch outputs Q and QN will both be high.
FIG. 3 depicts a "master-slave" register circuit comprising first gated-latch 10A, second gated-latch 10B, and inverter 11 which inverts the gate signal SYS.sub.-- CLK connected to gated-latch 10A. It is customary to refer to gated-latch 10A as the "master latch," and gated-latch 10B as the "slave latch."
When SYS.sub.-- CLK is low, the gate signal G to master latch 10A is high, which enables master latch output Q to follow the SYS.sub.-- DATA input. During this time (i.e., while SYS.sub.-- CLK is low), the gate signal G to slave latch 10B is low, which prevents the slave latch 10B output Q from changing. When SYS.sub.-- CLK changes to the logic high level, the master latch 10A gate signal G goes to logic low, which prevents any further changes at the master latch Q output, even if the master latch data input D (which is connected to SYS.sub.-- DATA) changes. During this time (i.e. when SYS.sub.-- CLK is high), the gate signal to slave latch 10B is high, which enables the slave latch Q output to take on the same value as the master latch Q output. The slave latch output Q is thus allowed to change only once per clock cycle in response to SYS.sub.-- CLK changing from low to high. When SYS.sub.-- CLK changes from low to high, the slave latch Q output is set to the value of the SYS.sub.-- DATA input immediately prior to SYS.sub.-- CLK going high.
Previous scannable register designs focused on functional test problems. See, e.g., "Eichelberger, E.B. and Williams, T.W., "A Logic Design Structure for LSI Testability", Journal of Design Automation and Fault Tolerant Computing, May 1978, pp. 165-178. The present invention addresses the problem of testing the delay associated with particular paths. Whereas special process test devices can be used to test whether a particular device can be operated at a particular speed, defects and variations across the chip or wafer are not detected by such devices. Applying test vectors at speed to the pins of a chip provides some delay test coverage, but it is difficult to generate the required vectors for specific paths inside the chip.
Accordingly, it is an object of the present invention to provide means for facilitating delay path testing between any two scannable registers. It is a further object of the present invention to provide a scannable register in which two different values can be stored in the scan register, the second value being transferred to the register's output on a rising clock edge, propagating through the combinational logic (i.e., the delay path), and being captured in a scannable register on the next rising clock edge. In addition, another object of the present invention is to provide a scannable register in which initial values are loaded into a slave-latch portion of the scannable register, while values which are to replace them are loaded into a master-latch portion of the same register. Special test signals should be provided which allow these two values to be loaded into the register. These special test signals should also provide means for triggering the transfer of data values from the master-latch to the slave-latch, through the delay path, and into a register. Path delays in excess of the time delay between the rising edges of the two clock pulses should be exposed. The present invention achieves these goals.